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| ice50 .............................................................................................. user guide
ice50 user guide i 2523a?avr?11/02 table of contents section 1 preface ................................................................................................. 1-1 1.1 about this manual .....................................................................................1-1 1.1.1 warnings ............................................................................................1-1 1.1.2 tips.....................................................................................................1-1 1.1.3 workaround ........................................................................................1-1 1.1.4 checklists ...........................................................................................1-1 1.1.5 related documentation ......................................................................1-2 1.2 ice50 firmware history ............................................................................1-2 1.2.1 version 1.0 .........................................................................................1-2 1.2.2 version 1.1 .........................................................................................1-2 1.2.3 version 1.2 .........................................................................................1-2 1.3 ice50 known issues.................................................................................1-2 1.3.1 user break in sleep mode..................................................................1-2 1.3.2 adc latch-up .....................................................................................1-2 1.3.3 user break..........................................................................................1-2 1.4 reporting problems ..................................................................................1-3 section 2 introduction ........................................................................................... 2-1 2.1 ice50 contents.........................................................................................2-1 2.2 ice50 features .........................................................................................2-2 2.3 system requirements...............................................................................2-3 2.3.1 hardware requirements.....................................................................2-3 2.3.2 software requirements ......................................................................2-3 2.3.3 target hardware requirements .........................................................2-3 2.3.4 operating conditions..........................................................................2-3 2.3.5 host interface .....................................................................................2-3 section 3 general description .............................................................................. 3-1 3.1 general hardware description..................................................................3-1 3.1.1 what is an in-circuit emulator?..........................................................3-1 3.2 main emulator unit....................................................................................3-2 3.2.1 emulator unit......................................................................................3-2 3.2.2 status leds........................................................................................3-2 table of contents ii ice50 user guide 2523a?avr?11/02 3.3 pod bay ...................................................................................................3-4 3.3.1 removing pod from pod bay ..........................................................3-4 3.3.2 inserting pod into pod bay ..............................................................3-4 3.3.3 expansion bay....................................................................................3-5 3.3.4 usb connector...................................................................................3-5 3.3.5 rs-232c connector ...........................................................................3-5 3.3.6 reset button.......................................................................................3-5 3.3.7 power switch......................................................................................3-5 3.3.8 power connector................................................................................3-6 3.4 personality adapter description................................................................3-6 3.4.1 personality adapter description .........................................................3-6 3.4.2 t26 personality adapter ......................................................................3-7 3.4.3 t28 and t29 personality adapter .........................................................3-8 3.4.4 m8 personality adapter ......................................................................3-8 3.4.5 m32 personality adapter ....................................................................3-9 3.4.6 m162 personality adapter ..................................................................3-9 3.4.7 m128 personality adapter ................................................................3-10 3.4.8 m169 personality adapter ................................................................3-10 3.5 pod description .....................................................................................3-11 3.5.1 pod description...............................................................................3-11 3.5.2 digital i/o..........................................................................................3-12 3.5.3 analog comparator ..........................................................................3-14 3.5.4 a/d converter...................................................................................3-14 3.6 power system description ......................................................................3-15 3.6.1 power supply ...................................................................................3-15 3.6.2 ice50 power system .......................................................................3-15 3.6.3 target application power requirements ..........................................3-16 3.7 probe description ...................................................................................3-17 3.7.1 probe description .............................................................................3-17 3.7.2 external clock signal .......................................................................3-18 3.7.3 internal clock signal provided by avr studio .................................3-18 3.7.4 external 32 khz rtc crystal............................................................3-19 3.7.5 internal rc oscillator .......................................................................3-19 3.7.6 external crystal and external resonator .........................................3-19 3.7.7 external rc oscillator ......................................................................3-19 3.8 test adapter ...........................................................................................3-19 3.8.1 using the test adapter.....................................................................3-20 table of contents ice50 user guide iii 2523a?avr?11/02 section 4 connecting ice50................................................................................. 4-1 4.1 connecting ice50 for emulation...............................................................4-1 4.2 connecting ice50 to host pc ...................................................................4-1 4.3 connecting the probe to the target board ...............................................4-1 4.3.1 connecting pdip adapters.................................................................4-1 4.3.2 connecting tqfp adapters ...............................................................4-3 4.4 ice50 power-up sequence.......................................................................4-4 section 5 configuring avr studio ........................................................................ 5-1 5.1 ice50 emulator options ...........................................................................5-1 5.2 avr studio configuration quick start guide............................................5-2 5.3 device selection .......................................................................................5-3 5.4 fuses and lock bits..................................................................................5-5 5.5 lock bits ...................................................................................................5-8 5.6 ice status .................................................................................................5-9 5.7 boot block options .................................................................................5-11 5.8 special ....................................................................................................5-12 5.9 downloading new parts for ice50..........................................................5-12 5.10 upgrading the ice50 firmware...............................................................5-13 section 6 special considerations ......................................................................... 6-1 6.1 electrical compatibility ..............................................................................6-1 6.1.1 power .................................................................................................6-1 6.1.2 i/o lines .............................................................................................6-1 6.2 sleep mode ...............................................................................................6-2 6.3 target hardware requirements................................................................6-2 6.4 clock options............................................................................................6-2 6.5 differences between emulator and part ...................................................6-2 section 7 trace..................................................................................................... 7-1 7.1 enabling trace in avr studio...................................................................7-1 7.2 the trace window ....................................................................................7-2 7.3 contents of trace window based on instruction (ice50).........................7-4 7.4 accessing external data memory (ice50 trace) ...................................7-14 7.5 interrupt handling (ice50 trace) ............................................................7-14 7.6 reset (ice50 trace) ...............................................................................7-15 7.7 save trace buffer to file (ice50) ...........................................................7-15 7.8 sleep (ice50 trace) ...............................................................................7-15 table of contents iv ice50 user guide 2523a?avr?11/02 section 8 troubleshooting .................................................................................... 8-1 8.1 troubleshooting guide..............................................................................8-1 ice50 user guide 1-1 rev. 2523a?avr?11/02 section 1 preface 1.1 about this manual this manual is using the nomenclature described in this section to show warnings, tips, workarounds etc. 1.1.1 warnings this manual contains important warnings to prevent damage to your system and the ice50. all the warnings are emphasized as shown in the example below. warning! this is a warning... please read all wa rnings carefully. 1.1.2 tips some sections contain useful tips for using the ice50. all the tips are emphasized as shown in the example below. tip! this is a tip... 1.1.3 workaround workaround! this is a workaround... 1.1.4 checklists once comfortable with the configurtion and use of the ice50, the checklists at the end of these sections can be used for fast setup of a new project. the checklists are of great help for getting the debugging system on-line without prob- lems. however, novice users should also check that the operating conditions of the target system are compliant to the requirements of ice50. this is described in the con- necting ice50 section. preface 1-2 ice50 user guide 2523a?avr?11/02 1.1.5 related documentation the following electronic documents from atmel ? are related to the use of the avr ? microcontrollers, and of the debugging tools. all documents can be found on the atmel products cd-rom enclosed in the ice50 kit. for more information and document updates, please visit our web site: www.atmel.com. avr studio ? user's guide. describes in detail how to use the avr studio debugging environment. describes in detail how to use the avr assembler. data sheets for the different avr devices. errata sheets for the different avr devices. application notes describing different application examples for the avr microcontrollers. describes in detail how to use the avr studio debugging environment. note: avr studio 4.0 or later is required for ice50 support. avr studio 3.x versions will not work with ice50! 1.2 ice50 firmware history there has been several releases of the ice50 firmware. 1.2.1 version 1.0 first released version. 1.2.2 version 1.1 errors in trace module fixed. version table readout in main module fixed. 1.2.3 version 1.2 all parts with adc: adc bit 3 and 4 where interchanged. this is now fixed on all parts with adc. trace of program counter is now correct in single step. brown-out detection (bod): selection of brown-out voltage is now enabled for all parts. mega8: reset disable fuse added to ice50 options. 1.3 ice50 known issues there are some known issues in the ice50 that users needs to be aware of. 1.3.1 user break in sleep mode user break in sleep mode is not supported. use an interrupt to wake up the part or a reset to reset the emulator. user break in sleep mode is not supported. workaround: a reset will break and reset the emulator. 1.3.2 adc latch-up the adc may latch-up if the target is powered before the ice. also make sure that no residual voltage is present on the adc input pins if the ice is not powered. 1.3.3 user break user break in sleep mode is not supported. use an interrupt to wake up the part or a reset to reset the emulator. preface ice50 user guide 1-3 2523a?avr?11/02 1.4 reporting problems problems with avr studio can be reported to avr@atmel.com. problems with beta releases can be reported to avrbeta@atmel.com. preface 1-4 ice50 user guide 2523a?avr?11/02 ice50 user guide 2-1 rev. 2523a?avr?11/02 section 2 introduction ATICE50 is an advanced in-circuit emulator that covers a wide range of the eight bits avr microcontrollers from atmel. this section gives a brief introduction to it?s features. 2.1 ice50 contents figure 2-1. the ATICE50 contains the following items: ice50 main unit/pod/two fpc (flexible printed circuit) cables & probe personality adapters for: ? atmega8 ? atmega16 ? atmega162 ? atmega32 ? atmega128 ?attiny26 introduction 2-2 ice50 user guide 2523a?avr?11/02 9-pin rs-232c cable usb cable power supply european power supply cable us power supply cable avr technical library cd-rom ? avr data sheets ? application notes ? avr studio 4.00 or later ice50 quick start guide 2.2 ice50 features the ice50 in-circuit emulator is a high-end emulator from atmel designed to emulate a wide range of avr devices. the ice50 is controlled by avr studio 4.0 or later. present, the following devices are supported: ?attiny26 ? atmega8 ? atmega16 ? atmega162 ? atmega32 ? atmega128 ? atmega169 ? atmega8515 ? atmega8535 the ice50 supports the following features: emulates all digital and analog peripherals target voltage range 2.2v - 5.5v full target frequency range for all supported devices watches trace buffer unlimited number of break points symbolic debugging support full visibility of and access to register file, sp, pc, and memories access to all i/o registers i/o configurable to run or halt in stopped mode cycle counter introduction ice50 user guide 2-3 2523a?avr?11/02 2.3 system requirements the following minimum requirements apply for the ice50. 2.3.1 hardware requirements for using the ice50 with avr studio, a pentium 233 mhz (or more) class personal computer with following specifications is recommended: 64 mbyte ram, or more 20 mbyte of free hard disk (hd) space cd-rom or internet access recommended screen resolution 1024x768 16650 compatible serial port (com port) avr studio v4.0 or later installed acrobat reader v4.0 or later installed (optional). 2.3.2 software requirements the following operating systems are currently supported by avr studio: windows nt ? version 3.51 (1) windows nt version 4.0 (1) windows ? 95 windows 98 (me) windows 2000 windows xp avr studio is always updated to fit new operating systems and versions. see avr studio user's guide for latest information. note: 1. windows nt 3.51 and windows nt 4.0 does not support usb communication. 2.3.3 target hardware requirements the target must be able to supply 2.2 - 5.5v @150ma. see table 3-6 for further information. 2.3.4 operating conditions operation temperature: 0c - 70c operating humidity: 10 - 90 % rh (non-condensing) supply voltage: +9.0v to +12.0v dc warning! violating the recommended operating conditions for the ice50 might cause incor- rect operation and damage the emulator. 2.3.5 host interface rs-232c @ 115200 bps, 1 start-, 8 data-, and 1 stop-bit, no parity with hardware hand- shaking. 9-pin female connector with rts and cts connected to support hardware handshaking. introduction 2-4 ice50 user guide 2523a?avr?11/02 ice50 user guide 3-1 rev. 2523a?avr?11/02 section 3 general description this setion describes the different components of the ATICE50 in detail. 3.1 general hardware description in this section a brief description of emulation is given, and a closer look at the parts that make up the ice50. 3.1.1 what is an in-circuit emulator? the ice50 is an in-circuit emulator. an emulator is a dedicated piece of hardware designed to ?emulate? the behaviour of another piece of hardware. in the case of the ice50, it is designed to behave as a wide range of avr devices. exact emulation is the goal for all emulators and the ice50 offers the highest possible level of compatibility. the ice50 emulator system consists of the following five modules: main emulator unit pod probe personality adapters test adapter general description 3-2 ice50 user guide 2523a?avr?11/02 3.2 main emulator unit the main emulator unit contains the ?brain? of the ice50. 3.2.1 emulator unit the main emulator unit is shown in figure 3-1. the main unit contains the control logic, and general hardware necessary to emulate an avr device. figure 3-1. ice50 main emulator status leds pod bay expansion bay usb connector rs-232c connector reset button power switch power connector 3.2.2 status leds there are three leds on the front of t he ice50 cabinet. one red, one red/green duo led and one green led. all these leds give important status information on the ice50 and which mode it is operating in. the picture below shows a close-up of the leds. when turning on power on the ice50 the normal led sequence will be as follows: 1. red power led turns on. 2. mode led turns on and is first red and next orange. 3. green status led turns on (after approx 15 seconds). this indicate that the unit is operating and ready for use. figure 3-2. emulator leds expansion bay pod bay leds power connector/ power switch reset button rs-232c/ usb general description ice50 user guide 3-3 2523a?avr?11/02 3.2.2.1 red power led the red led is the power indicator led. this will be lit if power on the ice50 is turned on and the power system is working correctly. if the led stays off after power on, make sure the power supply meets the requirements of the ice50. if using another power sup- ply than the one supplied with the ice50 make sure that the power polarity is correct. see the power system section for more details on power requirements. 3.2.2.2 multi color mode led the multicolor led displays information about which mode the ice50 is working in. dur- ing the startup sequence this led is first red, next orange. orange indicates that the emulator is in stopped mode. a green light indicates that the ice is in run mode. if the led turns red it indicates an emulator error. if this happens consult the troubleshooting guide. 3.2.2.3 green status led the green led will be turned on when the ice50 is ready for emulation. once the green led is on, the ice50 is ready for emulation. the led will flash during upgrading of the ice50. the led will be turned off during loading of a new part, and lit when the part is finished loading. if the led does not turn on after a power up sequence please consult the troubleshooting guide for possible solutions. figure 3-3. multi color mode table 3-1. led color definitions led meaning state description red power off power not connected, or ice50 turned off. on power connected, ice50 on and voltages ok. multi mode green run mode red error condition, if permanently lit. orange stopped mode green status off ice50 is initializing. on ice50 ready for emulation. blinking the led will flash when doing an upgrade. general description 3-4 ice50 user guide 2523a?avr?11/02 3.3 pod bay the ice50 has a very flexible architecture that will ensure a long product life. the differ- ent avr devices are characterised through their number of i/o pins and analog features. both the i/o pins and the analog features are implemented on the pod board. if new avr devices are made available to the market that contain i/o or analog features that cannot be emulated by the current pod, atmel is dedicated to create new pod modules that support the functionality of the new devices. 3.3.1 removing pod from pod bay if for some reason the pod must be removed from the pod bay, the recommended procedure is as described below. see also figure 3-4. 1. lift the pod on the front edge until a click is heard. the pod is now ready to be pulled up from the bay. 2. lift the pod out of the bay. figure 3-4. removing pod from pod bay without the pod connected, the ice50 will still be able to emulate core functions of the avr (e.g., timers). this feature can be useful in some debugging sessions. if the pod is inserted and there is no target power applied, the ice will be held in reset until target power is turned on. by disabling por and bod reset in ice50 other options dialog, ice50 will emulate correctly even if target power is not connected. 3.3.2 inserting pod into pod bay only original ice50 pods should be used with ice50 and care should be taken when placing or removing the pod. during normal use there is no need to remove the pod from the bay. if for some reason the pod is disconnected, the recommended procedure to re-insert the pod is as follows. see also figure 3-5. 1. place the pod in the ice50 pod connector. make sure that the connector male and female guides align. 2. use both hands and apply pressure on the upper half of the pod (on top of the connector). 3. after pressing the connector firmly in place, use one hand to apply pressure on the lower half of the pod. you will hear a click when the pod locks into position. general description ice50 user guide 3-5 2523a?avr?11/02 figure 3-5. inserting pod into pod bay 3.3.3 expansion bay the expansion connector is intended for future use, and not used in the current version of ice50. the pod placed in this socket is an empty pod enclosure and serves the purpose of protecting the expansion connector. 3.3.4 usb connector usb communication is supported in avr studio 4, build 181 and higher versions. usb drivers are found on the avr technical libr ary cd-rom. the usb port is shown in fig- ure 3-6 figure 3-6. usb-, rs-232c-communication, and reset button 3.3.5 rs-232c connector present, all communication between the ice50 and avr studio is done through a stan- dard rs-232c interface. this is the communication protocol used by com ports on pcs. the communication runs at 115200 bit/s, no parity, 8 data bits, 1 stop bit, (n81). for information on how to connect the ice50 to a pc see the connecting ice50 to pc section. see figure 3-6. 3.3.6 reset button by pressing the reset button on the ice50, a warm reset of the emulator is preformed. after approximately 15 seconds the configuration is completed, and the green status led will turn on indicating that the emulator is ready for use. see figure 3-6. 3.3.7 power switch the power switch is the main on/off switch for the ice50 emulator. switching this off will turn off power on the ice50. the ice50 will however remain grounded to the power supply. see figure 3-7. general description 3-6 ice50 user guide 2523a?avr?11/02 figure 3-7. power switch and connector 3.3.8 power connector the power connector on the ice50 system is a standard type with 2.1 mm center tap. ground should be connected to the center tap. for more information about power requirements and operating conditions see the power system description. see figure 3-7. 3.4 personality adapter description the personality adapters of the ice50 provides the physical adaption between the ice50 and the target device. 3.4.1 personality adapter description ice50 is supplied with a range of personality adapters. these adapters map the pinout from the ice50 pod to each of the microcontrollers it supports. each adapter includes an identification code that the ice50 and avr studio use for automatic device detec- tion. the ice50 package contains the following personality adapters: each adapter corresponds to one pinout type and supports one or more avr microcon- trollers. table 3-2 shows which devices are supported by the different personality adapters. table 3-2. personality adapters device use personality adapter named seral number atmega16 m32 a9902.3.1310.a atmega128 m128 w10635sdf atmega32 m32 a9902.3.1310.b attiny28/29 t28/t29 a9902.3.1350.b attiny26 t26 a9902.3.1370.a atmega162 m162 a9902.3.1300.b atmega8 m8 a9902.3.1390.c atmega169 m169 w10634sdf general description ice50 user guide 3-7 2523a?avr?11/02 3.4.1.1 connecting the personality adapter to the probe when connecting the personality adapter and the probe, make sure that the probe is connected with the correct orientation. the connectors will only fit when the boards have the correct orientation. on the personality adapters a circle indicates pin 1. make sure that the circle on the probe matches the circle on the personality adapter as shown in figure 3-8. figure 3-8. connecting personality adapter to probe 3.4.2 t26 personality adapter the t26 personality adapter is a pdip adapter for t26 devices. the footprint is a stan- dard 20-lead 0.300" wide, pdip package. if the target uses another package type, an additional adapter has to be purchased from a third party vendor. when connecting the personality adapter to the probe, make sure to align the circles on the probe and per- sonality adapter as shown above. figure 3-9. t26 personality adapter (1) note: 1. snr: a9902.3.1370.a 3.4.2.1 supported devices at t i n y 2 6 general description 3-8 ice50 user guide 2523a?avr?11/02 3.4.3 t28 and t29 personality adapter the t28 personality adapter is a pdip adapter for t28 devices. the footprint is a stan- dard 28-lead 0.300" wide, pdip package. if the target uses another package type, an additional adapter has to be purchased from a third party vendor. when connecting the personality adapter to the probe, make sure to align the circles on the probe and per- sonality adapter as shown above. figure 3-10. t28 and t29 personality adapter (1) note: 1. snr: a9902.3.1350.b 3.4.3.1 supported devices at t i n y 2 8 3.4.4 m8 personality adapter the m8 personality adapter is a pdip adapter for m8 devices. the footprint is a stan- dard 28-lead 0.300" wide, pdip package. if the target uses another package type, an additional adapter has to be purchased from a third party vendor. when connecting the personality adapter to the probe, make sure to align the circles on the probe and per- sonality adapter as shown above. figure 3-11. m8 personality adapter (1) note: 1. snr: a9902.3.1390.c 3.4.4.1 supported devices atmega8 general description ice50 user guide 3-9 2523a?avr?11/02 3.4.5 m32 personality adapter the m32 personality adapter is a pdip adapter for m32/m16 devices. the footprint is a standard 40-lead 0.600" wide, pdip package. if the target uses another package type, an additional adapter has to be purchased from a third party vendor. when connecting the personality adapter to the probe, make sure to align the circles on the probe and personality adapter as shown above. figure 3-12. m32 personality adapter (1) note: 1. snr: a9902.3.1310.b 3.4.5.1 supported devices atmega32/atmega16 3.4.6 m162 personality adapter the m162 personality adapter is a pdip adapter for m162 devices. the footprint is a standard 40-lead 0.600" wide, pdip package. if the target uses another package type, an additional adapter has to be purchased from a third party vendor. when connecting the personality adapter to the probe, make sure to align the circles on the probe and personality adapter as shown above. figure 3-13. m162 personality adapter (1) note: 1. snr: a9902.3.1300.b 3.4.6.1 supported devices atmega162 general description 3-10 ice50 user guide 2523a?avr?11/02 3.4.7 m128 personality adapter the m128 personality adapter is a tqfp64 adapter, and it consists of two modules. the bottom module has the tqfp footprint, and should be soldered on the target appli- cation. make sure to solder it with the correct orientation. pin 1 is indicated with a printed ?1? as shown here. once the bottom module is soldered into the application, connect the top module. make sure that pin 1 on the top module matches the pin 1 on the bottom module. once the personality adapter is securely mounted, place the probe on the personality adapter. the circle marked on the probe should align with pin 1 on the m128 adapter. figure 3-14. m128 personality adapter (1) note: 1. snr: w10635sdf 3.4.7.1 supported devices atmega128 3.4.8 m169 personality adapter figure 3-15. m169 personality adapterfigure 1 note: 1. snr: w10634sdf 3.4.8.1 supported devices atmega169 general description ice50 user guide 3-11 2523a?avr?11/02 3.5 pod description the ice50 pod implements all digital i/o and analog functionality of the current avr family of devices. if new avr devices are made available to the market that contain i/o or analog features that cannot be emulated by the current pod, atmel is dedicated to create new pod modules that support the functionality of the new devices. 3.5.1 pod description the ice50 pod is shown in figure 3-16. it connects to the main unit through two dock- ing connectors. when connecting or disconnecting the pod do not use excessive force as this might damage the pod. figure 3-16. ice50 pod the pod contains all analog and digital logic necessary to emulate the target avr device. the circuitry is designed to give as close as possible electrical characteristics as the real device. the pod emulates the following functions: digital i/o analog comparator a/d converter the ice50 is a jumperless design. all conf iguration of the pod is done through avr studio. no manual configuration of jumpers is necessary. general description 3-12 ice50 user guide 2523a?avr?11/02 3.5.2 digital i/o the digital io ports of the ice50 are realized as shown in figure 3-17 using cmos buff- ers and voltage converters. figure 3-17. digital i/o the propagation delay of the io ports are lar ger for the ice50 than for the actual emu- lated part. the diagram below shows the timing data for driving out and reading in a signal on the io ports of the emulator. the data direction register is assumed set to ?1? in figure 3-18. table 3-3 shows typical data. figure 3-18. data direction register pullup (ddrxy & portxy) ddrxy portxy pinxy pinkeepx v cc 330k 36k pxy v cc emulator v cc target level converter digital i/o t ilh portxy pxy t ohl t ihl t olh pinxy general description ice50 user guide 3-13 2523a?avr?11/02 notes: 1. tohl = time from clearing the port register to the output changes 2. tolh = time from setting the port register to the output changes 3. tihl = time from changing the input level to the pin signal changes (high to low) 4. tilh = time from changing the input level to the pin signal changes (low to high) figure 3-19 shows the timing data for tristati ng/driving the io pins. table 3-4 shows related typical data. figure 3-19. timing data notes: 1. tdzl = time from setting the ddr register to the output is driven low. 2. tdlz = time from clearing the ddr register to the output is tristated. 3. tdzh = time from setting the ddr register to the output is driven high. 4. tdhz = time from clearing the ddr register to the output is driven low. the drive capability of the output buffers are 24 ma at 3v v cc . this slightly exceeds the driving capability of the actual parts. the operating voltage range of the io circuits are 2 v cc to 5.5 v cc . at 2v v cc the buffers are able to sink 25 ma with a maximal output low voltage (volmax) of 1v. the hysteresis voltage for the input buffers are typically 0.8v at 3v v cc and 1.2v at 5.5v v cc . table 3-3. data direction delay typical value (2v target) typical value (5v target) t ohl (1) 13 ns 10 ns t olh (2) 13 ns 10 ns t ihl (3) 13 ns 10 ns t ilh (4) 13 ns 10 ns table 3-4. timing data delay typical value (2v target) typical value (5v target) t dzl (1) 15 ns 15 ns t dlz (2) 15 ns 15 ns t dzh (3) 15 ns 15 ns t dhz (4) 15 ns 15 ns ddrxy portxy pxy t dzl t dlz t dzh t dhz high z high z high z general description 3-14 ice50 user guide 2523a?avr?11/02 3.5.3 analog comparator the analog comparator is built around a high speed comparator and a cmos output buffer/voltage converter. figure 3-20 shows the analog comparator block diagram. the total propagation delay from the ain0 and ain1 pins to the internal aco signal is typi- cally 90ns, max 210ns. for parts, the total propagation delay from the ain0 and ain1 pins to the internal aco signal is typically 500 ns, max 750 ns. the comparator features an internal hysteresis of typical 1 mv, max 4 mv @ 25 c to ensure clean switching. figure 3-20. analog comparator block diagram 3.5.4 a/d converter the block diagram of the ice50 ad converter is shown in figure 3-21. figure 3-21. ice50 ad converter acme aden ain1 adc multiplexer output acbg 1.2v ain0 + - acd 100r aco analog comparator 330 ? 330 ? 330 ? 330 ? 330 ? 330 ? 330 ? 330 ? pos input mux neg input mux admux decoder 1.2v v cc v cc + - 10k 10k + - ref ref 1x/10x/100x 1x/2x adc multiplexer output 10-bit adc vin vref 330 ? 330 ? voltage reference selection aref out + - 10k 10k + - vref 2 q[0..9] a/d converter adc7 adc6 adc5 adc4 adc3 adc2 adc1 adc0 avcc aref 2.5v general description ice50 user guide 3-15 2523a?avr?11/02 the adc is built using analog multiplexers, programmable gain instrumentation amplifi- ers and a 10-bit successive approximation a/d converter. this construction should have the same performance as the actual part, but since the adc is located on the pod as an external construction the analog components will be more susceptible to ambient noise and noise from switching io lines. note: internal analog reference voltage is set to 2.5 volt when using the emulator. this differs from part which uses 2.56 v. due to this fact adc conversions done by the emulator using the internal analog reference voltage differ from the conver- sions done in part. all inputs to the adc have serial current limiting resistors of 330 ? . this is to protect the inputs of the adc circuit when the emulator is switched off and the target power is present. the outputs of the input multiplexers are clamped to v cc and gnd and thus when target v cc is present and the emulator power is turned off there will flow a current of approximately (vinput - 0.3v)/330 ? through each adc input pin. 3.6 power system description the ice50 needs external power in order to function. a switching power adapter is sup- plied with the unit. the power adapter will accept input voltages in the range of 100vac to 240vac and frequencies from 50hz to 60hz. this will cover most situations. 3.6.1 power supply figure 3-22. power supply the power supply delivered with ice50 is dimensioned to meet the requirements of the emulator. if another power supply is used, it should supply a voltage between 9 and 15 vdc, and a minimum of 20w. it connects to the main unit through a standard connector with 2.1 mm center tap. ground is connected to the center tap. 3.6.2 ice50 power system the ice50 has an internal power regulator designed to deliver regulated voltages for use by the ice itself. the power system is not designed to provide external power to the target application. general description 3-16 ice50 user guide 2523a?avr?11/02 3.6.3 target application power requirements the probe and parts of the pod are powered by the target application power system. the dynamic power requirements of the probe/po d will not differ significantly from the power requirements of the actual device. see below for power requirements. the static power requirement for the pod is listed in table 3-6. the target power system must be dimensioned to tolerate this current consumption. note: the digital i/o drive capabilities of the ice50 pod differ slightly from what can be expected in the actual device. for details on the digital i/o drive capabilities compared to the actual device, please see the digital i/o section of the pod description. table 3-5. power requirements power requirements power voltage requirements 9 - 15 vdc power consumption < 20 w target application voltage range 2.7 - 5.5 v table 3-6. target voltage target voltage ice50 (pod/probe) current consumption from target application, normal (typical) worst case 2.5v 5 ma 7 ma 3.3v 20 ma 30 ma 5.0v 85 ma 125 ma 5.5v 110 ma 165 ma general description ice50 user guide 3-17 2523a?avr?11/02 3.7 probe description the ice50 probe is the link between the flex cable going out from the pod and the per- sonaliy adapter that fits into the target application. the main purpose of the probe is to route all the signals from the flex cable to the appropriate pins of the personality adapter. in addition the probe implements current limitation on all the i/o pins in order to protect both the target and the pod. the probe also implements proper line termination in order to avoid ringing on high freuency signals. 3.7.1 probe description the probe contains clock driver circuitry for the ice50, voltage polarity and short circuit protection. figure 3-23 show a picture of the probe and a simplified block diagram of how the clock driver circuitry is implemented is shown in figure 3-24 and figure 3-25. by putting the clock driver circuitry on the probe (as close as possible to the target board) the best possible emulation of the avr clock options are achieved. figure 3-23. probe figure 3-24. timer oscillator timer oscillator drive enable output general description 3-18 ice50 user guide 2523a?avr?11/02 figure 3-25. external clock 3.7.1.1 available clock options the current version of the probe has some restrictions with regards to clock options support. the unsupported clock modes are quite easy to emulate with simple workarounds as described in section 3.7.6 and section 3.7.7. the probe version can be found on top of the back side of the probe (left side of the right picture above). 3.7.1.2 ice50 probe version a9902.3.1200.e version a9902.3.1200.e of the probe supports the following clock options: external clock signal internal clock signal provided by avr studio external 32 khz rtc crystal internal calibrated rc oscillator the following clock options are not supported by probe version a9902.3.1200.c. a description for workarounds for the unsupported clock modes can be found in section ?external crystal and external resonator? on page 19 and ?external rc oscillator? on page 19. 3.7.2 external clock signal an external clock signal can be applied to the xtal1 pin on the emulator probe. the emulator can then be set up to use this signal as the system clock. see device selection for a description of how to set up avr studio for this option. the clock signal must meet the conditions as shown in table 3-7. 3.7.3 internal clock signal provided by avr studio the emulator may be set up to run on an internal programmable clock. the frequency range of this programmable clock is 5 khz to 20 mhz. however, the maximum fre- quency cannot be set higher than the speed limit of the actual part. only certain output frequencies are possible to generate with highest accuracy. however the clock genera- tor generally produces an output frequency within 0.1% of the desired output frequency. if the target application should run on the same clock as the avr chip/emulator, the internal programmable clock may be driven out on the xtal2 pin. see section device selection for a description of how to set up the internal programmable clock. enable xtal2 enable xtal1 table 3-7. clock signal conditions value frequency 5khz to 20mhz duty cycle 50% absolute maximum inpu t voltage 1.8 - 7.0v recommended input voltage 1.8 - 5.5v minimum high level input voltage 1.7v maximum low level input voltage 0.5v general description ice50 user guide 3-19 2523a?avr?11/02 3.7.4 external 32 khz rtc crystal the asynchronous timers in the emulated part may be clocked by an external 32 khz crystal. this crystal should be connected to the tosc1 and tosc2 pins of the person- ality adapter. to ensure proper operation the crystal should be connected as close to the personality adapter as possible. the oscillator driver on the probe is designed to work with most parallel mode 32 khz crystals. 3.7.5 internal rc oscillator in avr studio the emulator may be set to run on an internal rc oscillator. see section device selection for a description of how to set up the internal rc oscillator. 3.7.6 external crystal and external resonator external crystal/resonator is not supported on the ice50 probe. instead, configure the emulator to use the internal programmable clock. the xtal1 pin will then be tri-stated. xtal2 pin will be enabled and the internal programmable clock is driven out on the xtal2 pin. see special section for a description of how to set up the xtal2 clock. 3.7.7 external rc oscillator external rc oscillator is not supported on the ice50 probe. instead, configure the emu- lator to use the internal programmable clock. the xtal1 and xtal2 pins will then be tristated. 3.8 test adapter ice50 is supplied with a test adapter. see figure 3-26. figure 3-26. test adapter (1) note: 1. snr: a9902.3.1400.a the adapter includes an identification code that the ice50 and avr studio uses for detection. the ice50 test adapter is used for the following tests: analog comparator analog digital converter i/o pins general description 3-20 ice50 user guide 2523a?avr?11/02 3.8.1 using the test adapter the test adapter must be connected to the probe. to start the test program open avr studio and select from the drop down menu: tools- >ice50 selftest. the window showing in figure 3-27 will appear: figure 3-27. start test program in avr studio the tests that require a test adapter connected to the probe are the ones marked on the list above. select the test that should be run, and press the ?run? button to start the test. finally, the test program will show the status of the test. note: avr studio 4.0 or later is required for ice50 support. avr studio 3.x versions will not work with ice50! tip! avr studio is constantly being updated. check for upgrades at www.atmel.com. ice50 user guide 4-1 rev. 2523a?avr?11/02 section 4 connecting ice50 ice50 connects to both the pc where the firmware development is being made and the target application. this section describes the connection procedure. 4.1 connecting ice50 for emulation this section will describe how to connect and configure the ice50 for correct operation. this task can be divided in the following tasks: 1. selecting correct personality adapter 2. connecting the probe to the target board 3. connecting ice50 to pc 4. correct power-up sequence 5. configuring avr studio please follow the above description to make sure that the ice50 is configured properly! 4.2 connecting ice50 to host pc the ice50 connects to the host pc through a standard com port. make sure that the ice50 is powered down before connecting the cable between the ice50 and the host pc. use the 9-pin rs-232c cable that is shipped with the ice50. connect the male cable connector to the ice50 and the female connector to the host pc. the communica- tion runs at 115200 bit/s, no parity, 8 data bits, 1 stop bit, (n81), and with hardware handshake. avr studio can not force control over a com port. if other equipment or software driv- ers have control of the com port (eg. irda , pda, scanner.. ) communication with the ice50 will fail. make sure that no other software has control of the com port that ice50 is connected to. note: the usb interface is not supported in the current version of the ice50. once the ice50 is connected to the host pc, continue with connecting the probe to the target board. 4.3 connecting the probe to the target board the probe is connected to the target board through one of the supplied personality adapters. to ensure correct operation make sure that the correct personality adapter is used. 4.3.1 connecting pdip adapters before connecting the ice50 to the target application, make sure that the ice50 and the target application are not powered. this also applies when removing the ice50. when connecting ice50 4-2 ice50 user guide 2523a?avr?11/02 connecting or disconnecting the ice50 from the host pc, make sure that the ice50 is not powered. 1. inserting the personality adapter. make sure that pin 1 on the personality adapter corresponds with pin 1 on the target socket/footprint. 2. mount the probe onto the personality adapter. do not use excessive force; the probe only fits one way into the personality adapter. use the circles on the per- sonality adapters and the probe to safely determine correct orientation. make sure that the probe is connected to the pod connector on the ice50. figure 4-1. connecting pdip adapters (part one of two) note: 1. place the personality adapter in the target application socket. make sure that the dot on the personality adapter match pin 1 in the target socket. figure 4-2. connecting pdip adapters (part two of two) note: 1. place the probe on the personality adapter. the circle on the probe should face in the same direction as the dot on the personality adapter. connecting ice50 ice50 user guide 4-3 2523a?avr?11/02 4.3.2 connecting tqfp adapters the m128 tqfp adapter consists of two parts: the bottom part that should be soldered into the target application, and the top part that interface with the ice50 probe. when mounting the tqfp adapter, make sure that the adapter is soldered into the application with the correct orientation. 1. start soldering the bottom part of the personality adapter on the target applica- tion. make sure that pin 1 on the adapter matches pin 1 in the target application. 2. place the tqfp top module on top of the soldered bottom module. again take care to place it with the correct orientation. 3. place the probe on the personality adapter. use low temperature solder and soldering iron when soldering the bottom part to the tar- get. this will ensure that the solder on the adapter is not removed during soldering. figure 4-3. connecting tqfp adapters (part one of three) note: 1. place and solder the bottom module. take care to place it with correct orientation. connecting ice50 4-4 ice50 user guide 2523a?avr?11/02 warning! every design precaution is taken so that the probe and ice50 pod should not be damaged if incorrectly placed. however, selecting wrong adapter, or placing the adapter with wrong orientation may damage the ice50 pod. connecting or disconnecting the pod or personality adapter while the target application is powered might damage the probe and/or the pod. once the probe and personality adapter are connected, continue by correct power-up sequence. 4.4 ice50 power-up sequence when the ice50 is properly connected to the target and the host pc, the power can be turned on. the following procedure is re commended to ensure proper communication between the ice50 and avr studio. power up ice50, wait for yellow led to be lit. power up target board. start avr studio. note: the equipment will not be harmed in any way if a different power up sequence is used, but since avr studio tries to detect peripherals when started, the ice50 will not be detected if not powered. once the power-up sequence is done, the next step is to start up and configure avr studio. for more informatio n on power supply requirements follow this link. ice50 user guide 5-1 rev. 2523a?avr?11/02 section 5 configuring avr studio when the ice50 is properly connected to the target application, the next step is to set up the correct device configuration in avr studio. this is required when an application project is opened for the first time, and can later be changed in the emulator options menu. the configuration is stored in a separate file, and will automatically be loaded when starting the project later. this section is divided in two subsections: 1. one quick start guide describing the procedure to get the avr studio configured. 2. one subsection describing all emulator options in detail. 5.1 ice50 emulator options device selection options fuses ice module/revision list special note: avr studio 4.0 or later is required for ice50 support. avr studio 3.x versions will not work with ice50! configuring avr studio 5-2 ice50 user guide 2523a?avr?11/02 5.2 avr studio configuration quick start guide follow the procedure described below to configure the ice50: 1. connect the ice50 and start avr studio. see connecting ice50 for a more detailed description. 2. select between creating a new or opening an existing avr assembler project. see picture below. 3. if you have already made an object file you can open this directly. see figure 5- 1. figure 5-1. welcome to avr studio 4 4. if a new project is chosen, type in the project name. check create initialfile if you would like an assembler file with the same name as the project. if you would like a folder created with the same name check this option. browse to select location for the project. see figure 5-2. figure 5-2. new project window configuring avr studio ice50 user guide 5-3 2523a?avr?11/02 5. press the next button. now select ice50 as target and then chose the part to emulate. press finish to complete the wizard. avr studio will now be ready for use. see figure 5-3. parts that are downloaded and available in ice50 are shown highlighted. if a part in grey colour is selected the tool for downloading new parts is launched. see download new parts for ice50. figure 5-3. avr studio 4 screenshot 5.3 device selection 1. in avr studio go to debug->ice50 options. device selection is highlighted and it is possible to choose from different parts in the pulldown menu. note the icon to the left for each part name. click this icon if this part is to be loaded into the ice50. a total of four part files can be contained in the ice50 at the same time. some part files contain two avr emulator parts. the status bar at the right side indicates how many part files ice50 contains. for atmega128 it is also possible to choose atmega103 compatibility mode. 2. select between the following clock sources:(this will affect the fuse settings for the actual part). ? internal xtal oscillator ? internal rc oscillator ? external clock 3. different start-up times can be selected from the start-up time pulldown menu. (this will affect the fuse settings for the actual part.) 4. part frequency can be selected from the frequency pulldown menu as shown in figure 5-4 or the frequency can be typed in the editor box. configuring avr studio 5-4 ice50 user guide 2523a?avr?11/02 figure 5-4. device selection in addition two buttons called ice reset and set default are located in the lower left cor- ner. see figure 5-4. the ice reset button resets the ice while the set default button loads the default settings. ice reset performs the same reset as the reset button on the back of the ice50. configuring avr studio ice50 user guide 5-5 2523a?avr?11/02 5.4 fuses and lock bits the fuse- and lock bit settings in the part can be viewed and configured from avr stu- dio. the fuse settings can only be viewed and not edited in the ?fuse and lock bit? view. configuration is performed in the other views. in avr studio go to debug->ice50 options. highlight fuses and lock bits. it is now possible to view 4 different settings. note that fuses marked with ?!? do not affect emulation. figure 5-5. fuse and lock bits settings 1. by pressing ?extended? fuse the tree expands and it is possible to see the set- tings for this fuse. ?0? indicates on or fuse programmed, ?1? indicates off. it is not possible to edit the fuse setting here. the extended fuses are available for selected parts. see the datasheet for the part when configuring the fuses. in this case the atmega128. the extended fuse is used to support special features. see figure 5-6. configuring avr studio 5-6 ice50 user guide 2523a?avr?11/02 figure 5-6. extended fuse settings 2. by pressing ?low fuse? the tree expands and it is possible to see the settings for this fuse. ?0? indicates on, ?1? indicates off. the fuse settings can not be edited here. see the datasheet for the part when configuring the fuses. see figure 5-7. figure 5-7. low fuse settings 3. by pressing ?high fuse? the tree expands and it is possible to see the settings for this fuse. ?0? indicates on, ?1? indicates off. the fuse settings can not be edited here. see the datasheet for the part when configuring the fuses. note that fuses marked with ?!? do not affect emulation. see figure 5-8. configuring avr studio ice50 user guide 5-7 2523a?avr?11/02 figure 5-8. high fuse settings tip! not all fuse settings are supported by the ice50. the following fuses are ignored: ? ocden. on chip debug is not available in ice50. ? spien. serial programming not available. ? eesave. not available in ice50. ? jtagen. not available in ice50. configuring avr studio 5-8 ice50 user guide 2523a?avr?11/02 5.5 lock bits by pressing lock bits the tree expands and it is possible to see the lock bit settings. ?0? indicates on, ?1? indicates off. the fuse settings can not be edited here. see the datasheet for the part when configuring the lock bits. see figure 5-9. figure 5-9. lock bits settings configuring avr studio ice50 user guide 5-9 2523a?avr?11/02 5.6 ice status in avr studio go to debug->ice50 options. highlight ice status. the report which appear describes the different modules with respect to software version and firmware version. see figure 5-10. in addition two buttons called ice reset and set default are located in the lower left corner. see figure below. the ice reset button performs a warm emulator reset and can be used instead of the reset button on the back of the ice50 while the set default button loads the default setting for the actual part. figure 5-10. ice status reports for the different fpga configuration files and the hardware revisions in the dif- ferent pcb's are also shown. see figure 5-11. configuring avr studio 5-10 ice50 user guide 2523a?avr?11/02 figure 5-11. ice staus window configuring avr studio ice50 user guide 5-11 2523a?avr?11/02 5.7 boot block options in avr studio go to debug->ice50 options. highlight boot block options. four different pulldown menus will appear. see figure 5-12. the four menus are: 1. boot size. select between the available boot sizes in the pulldown menu. 2. reset vector. select application or boot reset vector. 3. boot lock protection mode0, application section. select between four different types. see datasheet for the actual part for more information. 4. boot lock protection mode1, boot section. select between four different types. see datasheet for the actual part for more information. note: this menu is only available for avr parts with boot block. figure 5-12. boot block options note: avr studio 4.0 or later is required for ice50 support. avr studio 3.x versions will not work with ice50! configuring avr studio 5-12 ice50 user guide 2523a?avr?11/02 5.8 special special settings can be configured from avr studio. in avr studio go to debug->ice50 options. highlight other options. it is now possible to configure xram, reset sources and timer oscillator. see figure 5-13. xram: choose between emulate xram memory internally in ice50, or enable the avr external xram interface for using ram in the target application. reset sources: enable/disable por (power-o n reset), bod (brown-o ut detector), or external reset. timer oscillator: choose between internal or external. the two checkboxes in the upper right corner makes it possible to: disable sourcing of xtal2 clock . enable watchdog timer always on. watchdog ca be configured to break on watchdog overflow or reset on watchdog overflow. figure 5-13. special settings in addition two buttons called ice reset and set default are located in the lower left cor- ner. the ice reset button resets the ice while the set default button loads the default setting. ice reset performs the same reset as the reset button on the back of the ice50. 5.9 downloading new parts for ice50 avr studio will check if newer files are avai lable in the ice50 dat file, and prompt the user whether an upgrade should be performed. avr studio is continously updated. check the atmel web site, www.atmel.com, for upgrades. configuring avr studio ice50 user guide 5-13 2523a?avr?11/02 5.10 upgrading the ice50 firmware the ice50 firmware can be upgraded from avr studio. in avr studio go to tools ->ice50 upgrade. the window as shown in figure 5-14 will appear. figure 5-14. ice50 upgrade window from this window it is possible to select two buttons. the start upgrade button will per- form an upgrade of the ice50. note: if the skip version check checkbox is marked all modules and part files will be upgraded. if the allow downgrade checkbox is marked the ice 50 firmware can be downgraded. the ice50 info button shows the current firmware version in all modules and part files. see figure 5-15. configuring avr studio 5-14 ice50 user guide 2523a?avr?11/02 figure 5-15. version information ice50 user guide 6-1 rev. 2523a?avr?11/02 section 6 special considerations the ice50 accurately emulates most avr features. however, there are some differ- ences worth noting. clock options a/d converter accuracy differences from actual part electrical compatibility sleep mode target hardware requirements if you experience problems not described in this section, please see the troubleshooting section for more information. 6.1 electrical compatibility ice50 is created to emulate an actual avr device in detail. when it comes to electrical compatibility some issues must be considered. they are described in this section. 6.1.1 power the pod is protected against wrong polarity from the target power. in addition the pod will not be powered when ice50 power is disabled. see figure 6-1. figure 6-1. power 6.1.2 i/o lines the i/o lines are current limited by a thermistor. over voltage is suppressed by a schot- tky diode. this circuit can be seen in figure 6-2. ice on pod polarity protection pod target power special considerations 6-2 ice50 user guide 2523a?avr?11/02 figure 6-2. i/o lines 6.2 sleep mode when in sleep mode there will be no power reduction as can be seen in an actual part. 6.3 target hardware requirements the target must be able to supply 2.5 - 5.5v @ 200 ma. 6.4 clock options the current version of the ice50 probe has limited support for clock options. see available clock options for an overview of the supported modes. other modes can however easily be emulated using the modes above. 6.5 differences between emulator and part the atmega8 personality adapter (snr: a9902.3.1390.a) does not support external timer oscillator. adc internal voltage reference is 2.5v, and not 2.56v as in part. resetable fuse pod i/o probe i/o table 6-1. target voltage target voltage ice50 (pod/probe) current consumption from target application normal worst case 2.5v 5 ma 7 ma 3.3v 20 ma 30 ma 5.0v 85 ma 125 ma 5.5v 110 ma 165 ma ice50 user guide 7-1 rev. 2523a?avr?11/02 section 7 trace the ice50 contains a 144-bit wide, 128k levels deep trace buffer. this document describes the contents of the avr studio trace buffer view. 7.1 enabling trace in avr studio 1. to enable trace in avr studio select ?trace normal? from the trace toolbar pull- down menu. see figure 7-1. figure 7-1. enable trace 2. in the active source window select trace start and stop by pressing f8. press f8 once for trace to start at this line. press f8 twice for trace to end at this line. press f8 three times to remove trace. alternatively the icons on the trace tool- bar menu can be used instead of f8. the hand is equal to trace start and stop. the hands with red marks will remove all trace points. trace on is marked with a ?1? while trace off is marked by a ?1? with a red line across. see figure 7-2. figure 7-2. start and stop trace 3. it is possible to have several start and stop points. each pair of start and stop points will have an unique number (function id). in figure 7-3 two trace start/stop pair are shown (number 1 and 2). trace 7-2 ice50 user guide 2523a?avr?11/02 figure 7-3. multiple start and stop trace the function id numbers can be selected from the trace toolbar. in figure 7-4 function id ?2? is selected from a drop down menu. figure 7-4. function id selection 4. open trace window. 7.2 the trace window to view the trace output, select ?trace output? from the view menu or press the trace window icon in the trace toolbar. the trace window icon is located as number three from the right in figure 7-5. figure 7-5. trace output a window like illustrated in figure 7-6 will appear on the screen. the contents of the trace buffer will of course vary with the actual project. figure 7-6. trace buffer the trace function of the ice50 traces the program execution every clock cycle trace every single cycle in the execution. the trace view contains the columns described below. a more detailed description of the contents of each column for the individual avr instruction is found in the section: contents of trace window based on instruction. timestamp column: this column contains the value of the cycle counter at the time when the information was logged. note that the cycle counter has 41 bits so it will wrap at a value of 0x20000000000 or 2199023255552d . if executing with a clock frequency of 20 mhz, this means that the cycle counter will wrap every 30 hours. program memory address column (ins addr): this column contains the current value trace ice50 user guide 7-3 2523a?avr?11/02 of the program counter, i.e., it is the address in the program memory of the instruction currently being executed. for multicycle instructions, the contents of this column may contain other values. see the description of the various instruction. valid instruction (vi): this is a status flag which tells if the instruction is fetched and ready for execution. for multicycle instructions this bit will only be ?1? in the first cycle. instruction column (ins): this column contains the instruction word and the disassembled mnemonic representation of all instructions being executed. for multicycle instructions, this column will only contain information in the first cycle of the instruction. for the remaining cycles of the instructions, the column is left blank. data address column (dat.addr): this column contains the active address in the data memory space, and only contains information during some cycles in instructions reading from or writing to the data memory. see the description of the instructions to see what this field means for each instruction. register file low/high value column (rl &rh): for some of the instructions, the result being fed back to the register file is also sent to the trace buffer. for other instructions, this field does not contain any information. see the description of the instructions to see what this means in the various cases. register file valid signal (vr): this status bit indicates if the values on column rl and rh is valid in this cycle.. spare signals (s): for future use. status register column (sr): co ntains the avr status register. function id (ps): this column contains the function id number. interrupt acknowledge column: if an interrupt routine is invoked this column will contain a ?1? else a ?0?. trace 7-4 ice50 user guide 2523a?avr?11/02 7.3 contents of trace window based on instruction (ice50) as can be seen from enabling trace, the contents of the different columns varies with which instruction is being executed. this section describes how to interpret the contents of the trace buffer based on which instruction is being executed. some of the explanations are tagged with a number. this number indicates the cycle number in the instruction execution (important for multi-cycle instructions only). the term n/a is used when a field does not contain any valuable information. table 7-1. arithmetic and logic instructions instruction insta[0..15] pmem addr [pc[a0..22] reg.val regfilel[0..7] dat.addr ram_eeaddr [0..22] dat.val status register add rd,rr address of instruction result of addition n/a n/a z,c,n,v,s,h adc rd, rr address of instruction result of addition n/a n/a z,c,n,v,s,h adiw rdl,k 1. address of instruction 1. result of addition, low byte 1. n/a 1. n/a z,c,n,v,s 2. address of next instruction 2. result of addition, high byte 2. n/a 2. n/a sub rd, rr address of instruction result of subtraction n/a n/a z,c,n,v,s,h subi rd, k address of instruction result of subtraction n/a n/a z,c,n,v,s,h sbc rd, rr address of instruction result of subtraction n/a n/a z,c,n,v,s,h sbci rd, k address of instruction result of subtraction n/a n/a z,c,n,v,s,h sbiw rdl,k 1. address of instruction 1. result of subtraction, low byte 1. n/a 1. n/a z,c,n,v,s,h 2. address of next instruction 2. result of subtraction, high byte 2. n/a 2. n/a and rd, rr address of instruction result of logical and n/a n/a z,n,v,s andi rd, k address of instruction result of logical and n/a n/a z,n,v,s or rd,rr address of instruction result of logical or n/a n/a z,n,v,s ori rd, k address of instruction result of logical or n/a n/a z,n,v,s eor rd, rr address of instruction result of logical eor n/a n/a z,n,v,s com rd address of instruction result of complement n/a n/a z,c,n,v,s neg rd address of instruction result of negation n/a n/a z,c,n,v,s,h sbr rd,k will never appear (is disassembled to ori instruction) n/a n/a n/a z,n,v,s cbr rd,k will never appear (is disassembled to andi instruction) n/a n/a n/a z,n,v,s inc rd address of instruction result of incrementation n/a n/a z,n,v,s dec rd address of instruction result of decrementation n/a n/a z,n,v,s tst rd will never appear (is disassembled to and instruction) n/a n/a n/a z,n,v,s clr rd address of instruction result (always 0x00) n/a n/a z,n,v,s ser rd will never appear (is disassembled to ldi instruction) n/a n/a n/a n/a trace ice50 user guide 7-5 2523a?avr?11/02 mul rd, rr 1. address of instruction 2. address of next instruction 1. n/a 2. result of multiplication 1. n/a 2. n/a 1. n/a 2. n/a z,c muls rd, rr 1. address of instruction 1. n/a 1. n/a 1. n/a z,c 2. address of next instruction 2. result of multiplication 2. n/a 2. n/a mulsu rd, rr 1. address of instruction 1. n/a 1. n/a 1. n/a z,c 2. address of next instruction 2. result of multiplication 2. n/a 2. n/a fmul rd, rr 1. address of instruction 1. n/a 1. n/a 1. n/a z,c 2. address of next instruction 2. result of multiplication 2. n/a 2. n/a fmuls rd, rr 1. address of instruction 1. n/a 1. n/a 1. n/a z,c 2. address of next instruction 2. result of multiplication 2. n/a 2. n/a fmulsu rd, rr 1. address of instruction 1. n/a 1. n/a 1. n/a z,c 2. address of next instruction 2. result of multiplication 2. n/a 2. n/a table 7-1. arithmetic and logic instructions (continued) instruction insta[0..15] pmem addr [pc[a0..22] reg.val regfilel[0..7] dat.addr ram_eeaddr [0..22] dat.val status register trace 7-6 ice50 user guide 2523a?avr?11/02 table 7-2. data transfer instructions instruction insta[0..15] pmem addr [pc[a0..22] reg.val regfilel [0..7] dat.addr ram_eeaddr [0..22] dat.val status register mov rd, rr (1) address of instruction value loaded into register n/a n/a n/a movw rd, rr (1) address of instruction value loaded into rd+1 n/a n/a n/a ldi rd, k (1) address of instruction value loaded into register n/a n/a n/a ld rd, x (1) 1. address of instruction 1. n/a 1. n/a 1. n/a n/a 2. address of next instruction 2. value read 2. address read from (x) 2. address of next instruction ld rd, x+ (1) 1. address of instruction 1. n/a 1. n/a 1. n/a n/a 2. address of next instruction 2. value read 2. address read from (x) 2. value read ld rd, - x (1) 1. address of instruction 1. n/a 1. n/a 1. n/a n/a 2. address of next instruction 2. value read 2. address read from (x) 2. value read ld rd, y (1) 1. address of instruction 1. n/a 1. n/a 1. n/a n/a 2. address of next instruction 2. value read 2. address read from (y) 2. value read ld rd, y+ (1) 1. address of instruction 1. n/a 1. n/a 1. n/a n/a 2. address of next instruction 2. value read 2. address read from (y) 2. value read ld rd, - y (1) 1. address of instruction 1. n/a 1. n/a 1. n/a n/a 2. address of next instruction 2. value read 2. address read from (y) 2. value read ldd rd,y+q (1) 1. address of instruction 1. n/a 1. n/a 1. n/a n/a 2. address of next instruction 2. value read 2. address read from (y+q) 2. value read ld rd, z (1) 1. address of instruction 1. n/a 1. n/a 1. n/a n/a 2. address of next instruction 2. value read 2. address read from (z) 2. value read ld rd, z+ (1) 1. address of instruction 1. n/a 1. n/a 1. n/a n/a 2. address of next instruction 2. value read 2. address read from (z) 2. value read ld rd, -z (1) 1. address of instruction 1. n/a 1. n/a 1. n/a n/a 2. address of next instruction 2. value read 2. address read from (z) 2. value read ldd rd, z+q (1) 1. address of instruction 1. n/a 1. n/a) 1. n/a n/a 2. address of next instruction 2. value read 2. address read from (z+q 2. value read trace ice50 user guide 7-7 2523a?avr?11/02 lds rd, k (1) 1. address of instruction 1. n/a 1. n/a 1. n/a n/a 2. address of address-part of instruction 2. value read 2. address read from (k) 2. value read st x, rr (1) 1. address of instruction 1. n/a 1. n/a 1. n/a n/a 2. address of next instruction 2. n/a 2. address written to (x) 2. value written st x+, rr (1) 1. address of instruction 1. n/a 1. n/a 1. n/a n/a 2. address of next instruction 2. address written to (x) 2. value written st - x, rr (1) 1. address of instruction 1. n/a 1. n/a 1. n/a n/a 2. address of next instruction 2. n/a 2. address written to (x) 2. value written st y, rr (1) 1. address of instruction 1. n/a 1. n/a 1. n/a n/a 2. address of next instruction 2. n/a 2. address written to (y) 2. value written st y+, rr (1) 1. address of instruction 1. n/a 1. n/a 1. n/a n/a 2. address of next instruction 2. n/a 2. address written to (y) 2. value written st - y, rr (1) 1. address of instruction 1. n/a 1. n/a 1. n/a n/a 2. address of next instruction 2. n/a 2. address written to (y) 2. value written std y+q,rr 1. address of instruction 1. n/a 1. n/a 1. n/a n/a 2. address of next instruction 2. n/a 2. address written to (y+q) 2. value written st z, rr (1) 1. address of instruction 1. n/a 1. n/a 1. n/a n/a 2. address of next instruction 2. n/a 2. address written to (z) 2. value written st z+, rr (1) 1. address of instruction 1. n/a 1. n/a 1. n/a n/a 2. address of next instruction 2. n/a 2. address written to (z) 2. value written st -z, rr (1) 1. address of instruction 1. n/a 1. n/a 1. n/a n/a 2. address of next instruction 2. n/a 2. address written to (z) 2. value written std z+q,rr (1) 1. address of instruction 1. n/a 1. n/a 1. n/a n/a 2. address of next instruction 2. n/a 2. address written to (z+q) 2. value written sts k, rr (1) 1. address of instruction 1. n/a 1. n/a 1. n/a n/a 2. address of address-part of instruction 2. n/a 2. address written to (k) 2. value written table 7-2. data transfer instructions (continued) instruction insta[0..15] pmem addr [pc[a0..22] reg.val regfilel [0..7] dat.addr ram_eeaddr [0..22] dat.val status register trace 7-8 ice50 user guide 2523a?avr?11/02 note: 1. internal memory lpm 1. address of instruction 1. na 1. n/a 1. n/a n/a 2. address of next instruction 2. n/a 2. n/a 2. n/a 3. word address of data read 3. data read 3. n/a 3. n/a lpm rd, z 1. address of instruction 1. n/a 1. n/a 1. n/a n/a 2. address of next instruction 2. n/a 2. n/a 2. n/a 3. word address of data read 3. data read 3. n/a 3. n/a lpm rd, z+ 1. address of instruction 1. n/a 1. n/a 1. n/a n/a 2. address of next instruction 2. n/a 2. n/a 2. n/a 3. word address of data read 3. data read 3. n/a 3. n/a elpm 1. address of instruction 1. na 1. n/a 1. n/a n/a 2. address of next instruction 2. n/a 2. n/a 2. n/a 3. word address of data read 3. data read 3. n/a 3. n/a elpm rd, z 1. address of instruction 1. na 1. n/a 1. n/a n/a 2. address of next instruction 2. n/a 2. n/a 2. n/a 3. word address of data read 3. data read 3. n/a 3. n/a elpm rd, z+ 1. address of instruction 1. na 1. n/a 1. n/a n/a 2. address of next instruction 2. n/a 2. n/a 2. n/a 3. word address of data read 3. data read 3. n/a 3. n/a spm 1. address of instruction 1. n/a 1. n/a 1. n/a n/a 2. address of next instruction 2. n/a 2. n/a 2. n/a 3. word address of data write 3. data write 3. n/a 3. n/a in rd, p address of instruction value read from port 6 lsb give i/o address (a) value read from port n/a out p, rr address of instruction value written to port 6 lsb give i/o address (a) value written to port n/a push rr (1) 1. address of instruction 1. n/a 1. n/a 1. n/a n/a 2. address of next instruction 2. value pushed 2. stack pointer 2. value pushed pop rd (1) 1. address of instruction 1. n/a 1. n/a 1. n/a n/a 2. address of next instruction 2. value popped 2. stack pointer 2. value popped table 7-2. data transfer instructions (continued) instruction insta[0..15] pmem addr [pc[a0..22] reg.val regfilel [0..7] dat.addr ram_eeaddr [0..22] dat.val status register trace ice50 user guide 7-9 2523a?avr?11/02 table 7-3. branch instructions instruction insta [0..15] pmem addr [pc[a0..22] reg.val regfilel [0..7] dat.addr ram_eeaddr [0..22] dat.val status register rjmp 1. address of instruction 2. n/a 1. n/a 2. n/a 1. n/a 2. n/a 1. n/a 2. n/a n/a ijmp 1. address of instruction 2. n/a 1. n/a 2. n/a 1. n/a 2. destination address 1. n/a 2. n/a n/a jmp 1. address of instruction 2. address of address-part of instruction 3. n/a 1. n/a 2. n/a 3. n/a 1. n/a 2. n/a 3. n/a 1. n/a 2. n/a 3. n/a n/a rcall (1) 1. address of instruction 2. n/a 3. address of rcall destination 1. n/a 2. n/a 3. n/a 1. n/a 2. stack pointer 3. stack pointer 1. n/a 2. return address, low byte 3. return address, high byte n/a icall (1) 1. address of instruction 2. n/a 3. address of icall destination 1. n/a 2. n/a 3. n/a 1. n/a 2. stack pointer 3. stack pointer 1. n/a 2. return address, low byte 3. return address, high byte n/a call (1) 1. address of instruction 2. address of address-part of instruction 3. n/a 4. address of call destination 1. n/a 2. n/a 3. n/a 4. n/a 1. n/a 2. n/a 3. stack pointer 4. stack pointer 1. n/a 2. n/a 3. return address, low byte 4. return address, high byte n/a ret (1) 1. address of instruction 2. n/a 3. n/a 4. n/a 1. n/a 2. n/a 3. n/a 4. n/a 1. n/a 2. stack pointer 3. stack pointer 4. n/a 1. n/a 2. return address, high byte 3. return address, low byte 4. n/a n/a reti (1) 1. address of instruction 2. n/a 3. n/a 4. n/a 1. n/a 2. n/a 3. n/a 4. n/a 1. n/a 2. stack pointer 3. stack pointer 4. n/a 1. n/a 2.return address, high byte 3. return address, low byte 4. n/a n/a cpse 1. address of instruction (2) 1. n/a (2) 1. n/a (2) 1. n/a (2) n/a? 1. address of instruction (3) 2. address of skipped instruction (3) 1. n/a (3) 2. n/a (3) 1. n/a (3) 2. n/a (3) 1. n/a (3) 2. n/a (3) 1. address of instruction (4) 2. address of skipped instruction, first word (4) 3. address of skipped instruction, second word (4) 1. n/a (4) 2. n/a (4) 3. n/a (4) 1. n/a (4) 2. n/a (4) 3. n/a (4) 1. n/a (4) 2. n/a (4) 3. n/a (4) cp address of instruction n/a n/a n/a n/a cpc address of instruction n/a n/a n/a n/a cpi address of instruction n/a n/a n/a n/a trace 7-10 ice50 user guide 2523a?avr?11/02 sbrc 1. address of instruction (2) 1. n/a (2) 1. n/a (2) 1. n/a (2) n/a 1. address of instruction (3) 2. address of skipped instruction (3) 1. n/a (3) 2. n/a (3) 1. n/a (3) 2. n/a (3) 1. n/a (3) 2. n/a (3) 1. address of instruction (4) 2. address of skipped instruction, first word (4) 3. address of skipped instruction, second word (4) 1. n/a (4) 2. n/a (4) 3. n/a (4) 1. n/a (4) 2. n/a (4) 3. n/a (4) 1. n/a (4) 2. n/a (4) 3. n/a (4) sbrs 1. address of instruction (2) 1. n/a (2) 1. n/a (2) 1. n/a (2) n/a 1. address of instruction (3) 2. address of skipped instruction (3) 1. n/a (3) 2. n/a (3) 1. n/a (3) 2. n/a (3) 1. n/a (3) 2. n/a (3) 1. address of instruction (4) 2. address of skipped instruction, first word (4) 3. address of skipped instruction, second word (4) 1. n/a (4) 2. n/a (4) 3. n/a (4) 1. n/a (4) 2. n/a (4) 3. n/a (4) 1. n/a (4) 2. n/a (4) 3. n/a (4) sbic 1. address of instruction (2) 1. n/a (2) 1. 5 lsb give i/o address (a) (2) 1. n/a (2) n/a 1. address of instruction (3) 2. address of skipped instruction (3) 1. n/a (3) 2. n/a (3) 1. 5 lsb give i/o address (a) (3) 2. n/a (3) 1. n/a (3) 2. n/a (3) 1. address of instruction (4) 2. address of skipped instruction, first word (4) 3. address of skipped instruction, second word (4) 1. n/a (4) 2. n/a (4) 3. n/a (4) 1. 5 lsb give i/o address (a) (4) 2. n/a (4) 3. n/a (4) 1. n/a (4) 2. n/a (4) 3. n/a (4) sbis 1. address of instruction (2) 1. n/a (2) 1. 5 lsb give i/o address (a) (2) 1. n/a (2) n/a 1. address of instruction (3) 2. address of skipped instruction (3) 1. n/a (3) 2. n/a (3) 1. 5 lsb give i/o address (a) (3) 2. n/a (3) 1. n/a (3) 2. n/a (3) 1. address of instruction (4) 2. address of skipped instruction, first word (4) 3. address of skipped instruction, second word (4) 1. n/a (4) 2. n/a (4) 3. n/a (4) 1. 5 lsb give i/o address (a) (4) 2. n/a (4) 3. n/a (4) 1. n/a (4) 2. n/a (4) 3. n/a (4) brbs 1. address of instruction (6) 1. n/a (6) 1. n/a (6) 1. n/a (6) n/a 1. address of instruction (5) 2. n/a (5) 1. n/a (5) 2. n/a (5) 1. n/a (5) 2. n/a (5) 1. n/a (5) 2. n/a (5) brbc 1. address of instruction (6) 1. n/a (6) 1. n/a (6) 1. n/a (6) n/a 1. address of instruction (5) 2. n/a (5) 1. n/a (5) 2. n/a (5) 1. n/a (5) 2. n/a (5) 1. n/a (5) 2. n/a (5) breq 1. address of instruction (6) 1. n/a (6) 1. n/a (6) 1. n/a (6) n/a 1. address of instruction (5) 2. n/a (5) 1. n/a (5) 2. n/a (5) 1. n/a (5) 2. n/a (5) 1. n/a (5) 2. n/a (5) table 7-3. branch instructions (continued) instruction insta [0..15] pmem addr [pc[a0..22] reg.val regfilel [0..7] dat.addr ram_eeaddr [0..22] dat.val status register trace ice50 user guide 7-11 2523a?avr?11/02 brne 1. address of instruction (6) 1. n/a (6) 1. n/a (6) 1. n/a (6) n/a 1. address of instruction (5) 2. n/a (5) 1. n/a (5) 2. n/a (5) 1. n/a (5) 2. n/a (5) 1. n/a (5) 2. n/a (5) brcs 1. address of instruction (6) 1. n/a (6) 1. n/a (6) 1. n/a (6) n/a 1. address of instruction (5) 2. n/a (5) 1. n/a (5) 2. n/a (5) 1. n/a (5) 2. n/a (5) 1. n/a (5) 2. n/a (5) brcc 1. address of instruction (6) 1. n/a (6) 1. n/a (6) 1. n/a (6) n/a 1. address of instruction (5) 2. n/a (5) 1. n/a (5) 2. n/a (5) 1. n/a (5) 2. n/a (5) 1. n/a (5) 2. n/a (5) brsh 1. address of instruction (6) 1. n/a (6) 1. n/a (6) 1. n/a (6) n/a 1. address of instruction (5) 2. n/a (5) 1. n/a (5) 2. n/a (5) 1. n/a (5) 2. n/a (5) 1. n/a (5) 2. n/a (5) brlo 1. address of instruction (6) 1. n/a (6) 1. n/a (6) 1. n/a (6) n/a 1. address of instruction (5) 2. n/a (5) 1. n/a (5) 2. n/a (5) 1. n/a (5) 2. n/a (5) 1. n/a (5) 2. n/a (5) brmi 1. address of instruction (6) 1. n/a (6) 1. n/a (6) 1. n/a (6) n/a 1. address of instruction (5) 2. n/a (5) 1. n/a (5) 2. n/a (5) 1. n/a (5) 2. n/a (5) 1. n/a (5) 2. n/a (5) brpl 1. address of instruction (6) 1. n/a (6) 1. n/a (6) 1. n/a (6) n/a 1. address of instruction (5) 2. n/a (5) 1. n/a (5) 2. n/a (5) 1. n/a (5) 2. n/a (5) 1. n/a (5) 2. n/a (5) brge 1. address of instruction (6) 1. n/a (6) 1. n/a (6) 1. n/a (6) n/a 1. address of instruction (5) 2. n/a (5) 1. n/a (5) 2. n/a (5) 1. n/a (5) 2. n/a (5) 1. n/a (5) 2. n/a (5) brlt 1. address of instruction (6) 1. n/a (6) 1. n/a (6) 1. n/a (6) n/a 1. address of instruction (5) 2. n/a (5) 1. n/a (5) 2. n/a (5) 1. n/a (5) 2. n/a (5) 1. n/a (5) 2. n/a (5) brhs 1. address of instruction (6) 1. n/a (6) 1. n/a (6) 1. n/a (6) n/a 1. address of instruction (5) 2. n/a (5) 1. n/a (5) 2. n/a (5) 1. n/a (5) 2. n/a (5) 1. n/a (5) 2. n/a (5) brhc 1. address of instruction (6) 1. n/a (6) 1. n/a (6) 1. n/a (6) n/a 1. address of instruction (5) 2. n/a (5) 1. n/a (5) 2. n/a (5) 1. n/a (5) 2. n/a (5) 1. n/a (5) 2. n/a (5) brts 1. address of instruction (6) 1. n/a (6) 1. n/a (6) 1. n/a (6) n/a 1. address of instruction (5) 2. n/a (5) 1. n/a (5) 2. n/a (5) 1. n/a (5) 2. n/a (5) 1. n/a (5) 2. n/a (5) brtc 1. address of instruction (6) 1. n/a (6) 1. n/a (6) 1. n/a (6) n/a 1. address of instruction (5) 2. n/a (5) 1. n/a (5) 2. n/a (5) 1. n/a (5) 2. n/a (5) 1. n/a (5) 2. n/a (5) table 7-3. branch instructions (continued) instruction insta [0..15] pmem addr [pc[a0..22] reg.val regfilel [0..7] dat.addr ram_eeaddr [0..22] dat.val status register trace 7-12 ice50 user guide 2523a?avr?11/02 notes: 1. stack in internal memory 2. condition not met (no skip) 3. condition met, skippin g 1 word instruction 4. condition met, skippin g 2 word instruction 5. branch taken 6. branch not taken brvs 1. address of instruction (6) 1. n/a (6) 1. n/a (6) 1. n/a (6) n/a 1. address of instruction (5) 2. n/a (5) 1. n/a (5) 2. n/a (5) 1. n/a (5) 2. n/a (5) 1. n/a (5) 2. n/a (5) brvc 1. address of instruction (6) 1. n/a (6) 1. n/a (6) 1. n/a (6) n/a 1. address of instruction (5) 2. n/a (5) 1. n/a (5) 2. n/a (5) 1. n/a (5) 2. n/a (5) 1. n/a (5) 2. n/a (5) brie 1. address of instruction (6) 1. n/a (6) 1. n/a (6) 1. n/a (6) n/a 1. address of instruction (5) 2. n/a (5) 1. n/a (5) 2. n/a (5) 1. n/a (5) 2. n/a (5) 1. n/a (5) 2. n/a (5) brid 1. address of instruction (6) 1. n/a (6) 1. n/a (6) 1. n/a (6) n/a 1. address of instruction (5) 2. n/a (5) 1. n/a (5) 2. n/a (5) 1. n/a (5) 2. n/a (5) 1. n/a (5) 2. n/a (5) table 7-3. branch instructions (continued) instruction insta [0..15] pmem addr [pc[a0..22] reg.val regfilel [0..7] dat.addr ram_eeaddr [0..22] dat.val status register trace ice50 user guide 7-13 2523a?avr?11/02 table 7-4. bit and bit-test instructions instruction insta [0..15] pmem addr [pc [a0..22] reg.val regfilel [0..7] dat.addr ram_eeaddr[0..22] dat.val status register lsl address of instruction y/n n/a n/a z,c,n,v lsr address of instruction y/n n/a n/a z,c,n,v rol address of instruction y/n n/a n/a z,c,n,v ror address of instruction y/n n/a n/a z,c,n,v asr address of instruction y/n n/a n/a z,c,n,v swap address of instruction y/n n/a n/a n/a bset address of instruction n/a n/a n/a z,c,n,v,h bclr address of instruction n/a n/a n/a z,c,n,v,h sbi 1. address of instruction 2. address of next instruction 1. n/a 2. n/a 1. y/n 2. y/n 1. y/n 2. y/n n/a cbi 1. address of instruction 2. address of next instruction 1. n/a 2. n/a 1. y/n 2. y/n 1. y/n 2. y/n n/a bst address of instruction n/a n/a n/a t bld address of instruction y/n n/a n/a n/a sec address of instruction n/a n/a n/a c clc address of instruction n/a n/a n/a c sen address of instruction n/a n/a n/a n cln address of instruction n/a n/a n/a n sez address of instruction n/a n/a n/a z clz address of instruction n/a n/a n/a z sei address of instruction n/a n/a n/a i cli address of instruction n/a n/a n/a i ses address of instruction n/a n/a n/a s cls address of instruction n/a n/a n/a s sev address of instruction n/a n/a n/a v clv address of instruction n/a n/a n/a v set address of instruction n/a n/a n/a t clt address of instruction n/a n/a n/a t seh address of instruction n/a n/a n/a h clh address of instruction n/a n/a n/a h trace 7-14 ice50 user guide 2523a?avr?11/02 7.4 accessing external data memory (ice50 trace) instructions that are accessing data memory have different timing based on whether the memory is internal or external. for external memory accesses, the timing is again dependent on the number of wait states. this document does not describe the exact timings of these instructions, but they are fairly similar to those described above. a full description of the timing of these instructions can be found in contents of trace window based on instruction. it applies to the following instructions: ld (various forms), ldd (various forms), st (various forms), std (various forms), lds, sts, rcall, icall, call, ret, reti, push, pop. 7.5 interrupt handling (ice50 trace) interrupts are asynchronous events to the regular program flow. there is no instruction associated with the start of the processor handling an interrupt. however, once the pro- cessor has stored the return address to the stack, it will start to execute code from the interrupt vector address. an example is shown in below (figure 7-7 shows the code being executed), where an interrupt occurs during the execution of the instruction rjmp -0x0001. the interrupt acknowledge (ia) flag is set to ?1? as can be seen in figure 7-8. when this instruction is completed (two cycle instruction), it can be observed that the program counter is written to the stack at addresses 0x2f before it starts executing from the interrupt vector (in this case, interrupt vector 0x000013). after the (in this case very simple) interrupt program has completed, execution resumes. figure 7-7. example code table 7-5. mcu control instructions instruction insta [0..15] pmem addr [pc [a0..22] reg.val regfilel [0..7] dat.addr ram_eeaddr [0..22] dat.val status register nop address of instruction n/a n/a n/a n/a sleep address of instruction n/a n/a n/a n/a wdr address of instruction n/a n/a n/a n/a break address of instruction n/a n/a n/a n/a trace ice50 user guide 7-15 2523a?avr?11/02 figure 7-8. trace window output 7.6 reset (ice50 trace) an external reset, bod (brown-out detection) or a watchdog reset while trace is enabled will be traced in the trace window. 7.7 save trace buffer to file (ice50) the trace buffer can be dumped to a file. this function is available from the menu file- >save as. note that the trace window must be the active window. 7.8 sleep (ice50 trace) if trace is enabled when the microcontroller enters sleep mode, sleep will be logged into the trace buffer. this applies to all sleep modes. note, however, that the time stamp still counts while the microcontroller is asleep, and this can be used to measure how long the microcontroller has been asleep when it is woken up. the trace buffer will be filled with sleep instructions for each cycle as long as the microcontroller is in sleep mode. trace 7-16 ice50 user guide 2523a?avr?11/02 ice50 user guide 8-1 rev. 2523a?avr?11/02 section 8 troubleshooting the troubleshooting guide gives advise if errors occurs. 8.1 troubleshooting guide leds ? red power led does not turn on. see power supply trouble ? multi color led turns red (error led lights up). see configuration error ? green led does not light up. start avr studio and try to change part. power supply trouble ? check that power supply is connected ? check for wrong polarity ? check that the power source is not too weak ? power switch doesn't work configuration error ? not all modules have signed on. see ice status. check if a module is missing. a module not signed on will report a zero in the version field. communication errors ? check that the serial cable is connected. ? check that the pod is properly connected. see inserting pod into pod bay ? can't establish communication. check if other equipment has control over the com port, irda etc. ? cycle power and restart avr studio ? do no use serial port i/o card or usb to serial adapter ? usb communication is not yet supported troubleshooting 8-2 ice50 user guide 2523a?avr?11/02 printed on recycled paper. 2523a?avr?11/02 /0m ? atmel corporation 2002. atmel corporation makes no warranty for the use of its products, other than those expressly contained in the company?s standard warranty which is detailed in atmel?s terms and conditions located on the company?s web site. the company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without n otice, and does not make any commitment to update the information contained herein. no licenses to patents or other intellectual property of at mel are granted by the company in connection with the sale of atmel products, expressly or by implication. atmel?s products are not authorized for use as critical components in life support devices or systems. atmel headquarters atmel operations corporate headquarters 2325 orchard parkway san jose, ca 95131 tel 1(408) 441-0311 fax 1(408) 487-2600 europe atmel sarl route des arsenaux 41 case postale 80 ch-1705 fribourg switzerland tel (41) 26-426-5555 fax (41) 26-426-5500 asia room 1219 chinachem golden plaza 77 mody road tsimhatsui east kowloon hong kong tel (852) 2721-9778 fax (852) 2722-1369 japan 9f, tonetsu shinkawa bldg. 1-24-8 shinkawa chuo-ku, tokyo 104-0033 japan tel (81) 3-3523-3551 fax (81) 3-3523-7581 memory 2325 orchard parkway san jose, ca 95131 tel 1(408) 441-0311 fax 1(408) 436-4314 microcontrollers 2325 orchard parkway san jose, ca 95131 tel 1(408) 441-0311 fax 1(408) 436-4314 la chantrerie bp 70602 44306 nantes cedex 3, france tel (33) 2-40-18-18-18 fax (33) 2-40-18-19-60 asic/assp/smart cards zone industrielle 13106 rousset cedex, france tel (33) 4-42-53-60-00 fax (33) 4-42-53-60-01 1150 east cheyenne mtn. blvd. colorado springs, co 80906 tel 1(719) 576-3300 fax 1(719) 540-1759 scottish enterprise technology park maxwell building east kilbride g75 0qr, scotland tel (44) 1355-803-000 fax (44) 1355-242-743 rf/automotive theresienstrasse 2 postfach 3535 74025 heilbronn, germany tel (49) 71-31-67-0 fax (49) 71-31-67-2340 1150 east cheyenne mtn. blvd. colorado springs, co 80906 tel 1(719) 576-3300 fax 1(719) 540-1759 biometrics/imaging/hi-rel mpu/ high speed converters/rf datacom avenue de rochepleine bp 123 38521 saint-egreve cedex, france tel (33) 4-76-58-30-00 fax (33) 4-76-58-34-80 e-mail literature@atmel.com web site http://www.atmel.com at m e l ? , avr ? , and avr studio ? are the registered trademarks of atmel corporation. microsoft ? , windows ? , and windows nt ? are the registered trademarks of microsoft corporation. other terms and product names may be the trademarks of others. |
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